Designing of Low Power CNTFET based D Flip-Flop using Sleep Transistor Technique

Digital designs in this era require small size and low power components. Scaling of CMOS technology results into various short and narrow geometry effects. One of those effects is subthreshold current (leakage current) which results into unnecessary power dissipation. CNTFET (Carbon Nanotube FET) is a novel approach to solve the problem of scaling. Leakage current power dissipation is reduced by sleep transistor configuration. Flip Flops are an essential part of digital designs. Reduction of power consumption in a Flip Flop is highly desirable. This paper is intended to accomplish a systematic analysis of low power consumption positive edge triggered D Flip Flop made using CNTFETs and in sleep transistor configuration. The proposed circuit has less power dissipation and can be used efficiently with low power circuitry. This proposed work is then compared with the performance analysis of conventional Complementary Metal Oxide Semiconductor and Carbon Nanotube FET circuit designs. The overall simulation and computation is performed using HSPICE.

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Avichal Sahai, Vikas Sharma,”Design of Low Power CNTFET Based D Flip Flop using Sleep Transistor Technique”, volume -4 ,issue 4, IJERT.