Designing of Low Power CNTFET Based D Flip-Flop using Forced Stack Technique

Low Power devices in small packages is the need of present and future electronic devices. Electronics Industry is making devices which can be planted in human bodies. CMOS Technology won‟t be able to deliver such devices because it shows short channel effects in Nano scale. So, to overcome the problems of CMOS technology we use CNTs (Carbon Nano Tubes). In electronic devices, power is consumed by various elements like flip-flop, latches, clock sources. So in order to reduce power of a system we used to reduce power consumed by flip-flops.
In this paper we design an existing flip-flop “Low power clocked pass transistor flip-flop (LCPTFF)” on CNTFET using Stanford CNTFET model for reference. We propose a design of CNTFET based Forced Stack Low Power Clocked Pass Transistor Flip-Flop (CN-FS-LCPTFF) and observe 12% to 25% power reduction in various conditions like temperature change, CNTFET diameter change, and different voltage supply.

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Vikas Sharma, Umesh Dutta, “Designing of Low Power CNTFET Based D Flip-Flop Using Forced Stack Technique”Vol. 5 – Issue 4 (April – 2015), International Journal of Engineering Research and Applications (IJERA) , ISSN: 2248-9622 , www.ijera.com

Designing of Low Power CNTFET Based D Flip-Flop using Forced Stack Technique

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Designing of Low Power CNTFET based D Flip-Flop using Sleep Transistor Technique

Digital designs in this era require small size and low power components. Scaling of CMOS technology results into various short and narrow geometry effects. One of those effects is subthreshold current (leakage current) which results into unnecessary power dissipation. CNTFET (Carbon Nanotube FET) is a novel approach to solve the problem of scaling. Leakage current power dissipation is reduced by sleep transistor configuration. Flip Flops are an essential part of digital designs. Reduction of power consumption in a Flip Flop is highly desirable. This paper is intended to accomplish a systematic analysis of low power consumption positive edge triggered D Flip Flop made using CNTFETs and in sleep transistor configuration. The proposed circuit has less power dissipation and can be used efficiently with low power circuitry. This proposed work is then compared with the performance analysis of conventional Complementary Metal Oxide Semiconductor and Carbon Nanotube FET circuit designs. The overall simulation and computation is performed using HSPICE.

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Avichal Sahai, Vikas Sharma,”Design of Low Power CNTFET Based D Flip Flop using Sleep Transistor Technique”, volume -4 ,issue 4, IJERT.

Designing of Low Power CNTFET based D Flip-Flop using Sleep Transistor Technique

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