Showing posts with label VLSI. Show all posts
Showing posts with label VLSI. Show all posts

Friday, 1 May 2015

Low Power devices in small packages is the need of present and future electronic devices. Electronics Industry is making devices which can be planted in human bodies. CMOS Technology won‟t be able to deliver such devices because it shows short channel effects in Nano scale. So, to overcome the problems of CMOS technology we use CNTs (Carbon Nano Tubes). In electronic devices, power is consumed by various elements like flip-flop, latches, clock sources. So in order to reduce power of a system we used to reduce power consumed by flip-flops.
In this paper we design an existing flip-flop “Low power clocked pass transistor flip-flop (LCPTFF)” on CNTFET using Stanford CNTFET model for reference. We propose a design of CNTFET based Forced Stack Low Power Clocked Pass Transistor Flip-Flop (CN-FS-LCPTFF) and observe 12% to 25% power reduction in various conditions like temperature change, CNTFET diameter change, and different voltage supply.


Vikas Sharma, Umesh Dutta, “Designing of Low Power CNTFET Based D Flip-Flop Using Forced Stack Technique”Vol. 5 – Issue 4 (April – 2015), International Journal of Engineering Research and Applications (IJERA) , ISSN: 2248-9622 , www.ijera.com

Designing of Low Power CNTFET Based D Flip-Flop using Forced Stack Technique

Digital designs in this era require small size and low power components. Scaling of CMOS technology results into various short and narrow geometry effects. One of those effects is subthreshold current (leakage current) which results into unnecessary power dissipation. CNTFET (Carbon Nanotube FET) is a novel approach to solve the problem of scaling. Leakage current power dissipation is reduced by sleep transistor configuration. Flip Flops are an essential part of digital designs. Reduction of power consumption in a Flip Flop is highly desirable. This paper is intended to accomplish a systematic analysis of low power consumption positive edge triggered D Flip Flop made using CNTFETs and in sleep transistor configuration. The proposed circuit has less power dissipation and can be used efficiently with low power circuitry. This proposed work is then compared with the performance analysis of conventional Complementary Metal Oxide Semiconductor and Carbon Nanotube FET circuit designs. The overall simulation and computation is performed using HSPICE.


Avichal Sahai, Vikas Sharma,”Design of Low Power CNTFET Based D Flip Flop using Sleep Transistor Technique”, volume -4 ,issue 4, IJERT.

Designing of Low Power CNTFET based D Flip-Flop using Sleep Transistor Technique

Saturday, 4 October 2014

Carbon Nanotube Field Effect Transistor(CNTFET) is an promising alternative of an conventional CMOS technology in future. improvement in integration densities in past few years is remarkable but aggressive scaling of these MOS devices reaching to its limit. so the CNT replaces the isilicon so the CNTFET replaces the MOSFETs. 

Stanford university made an CNTFET model which we are using here. The codes are same as for MOSFET but the parameters need to be change like here Dcnt (diameter) of the CNT plays a role like L in the MOSFET.

SETUP: First we need to setup the the tools for CNTFET.
  • Install the HSPICE in your system 
  • download the library of CNTFET from standford university website. or CLICK HERE
  • make a directory with the name of project and paste all the file in the project from the package you downloaded from stanford university
WRITE THE CODE: Now write the code for the circuit in my case i am writing a code for an inverter.

***************************************************
***************************************************
*For optimal accuracy, convergence, and runtime
***************************************************
.options POST
.options AUTOSTOP
.options INGOLD=2     DCON=1
.options GSHUNT=1e-12 RMIN=1e-15
.options ABSTOL=1e-5  ABSVDC=1e-4
.options RELTOL=1e-2  RELVDC=1e-2
.options NUMDGT=4     PIVOT=13

.param   TEMP=27
***************************************************


***************************************************
*Include relevant model files
***************************************************
.lib 'CNFET.lib' CNFET
***************************************************
*Some CNFET parameters:


.param Ccsd=0      CoupleRatio=0
.param m_cnt=1     Efo=0.6    
.param Wg=0        Cb=40e-12
.param Lg=32e-9    Lgef=100e-9
.param Vfn=0       Vfp=0
.param m=19        n=0       
.param Hox=4e-9    Kox=16

***********************************************************************
* Define power supply
***********************************************************************


*Vdd     1     0     0.9



***********************************************************************
* Main Circuits
***********************************************************************
* nFET

X2 Out N_1 Gnd Gnd NCNFET Lch=Lg  Lgeff='Lgef' Lss=32e-9  Ldd=32e-9 
+ Kgate='Kox' Tox='Hox' Csub='Cb' Vfbn='Vfn' Dout=1  Sout=0  Pitch=20e-9  n1=m  n2=n  tubes=3

* pFET

X1 Out N_1 Vdd Vdd PCNFET Lch=Lg  Lgeff='Lgef' Lss=32e-9  Ldd=32e-9 
+ Kgate='Kox' Tox='Hox' Csub='Cb' Vfbp='Vfp' Dout=1  Sout=0  Pitch=20e-9  n1=m  n2=n  tubes=3

VVoltageSource_1 Vdd Gnd  DC 0.9
VVoltageSource_2 N_1 Gnd  PULSE(0 0.9 0n 5n 5n 50n 100n)

***********************************************************************

.tran 1n 500n

.MEASURE avg_pow AVG power FROM=1n TO=500n

.MEASURE TRAN t1 TRIG V(N_1) VAL = 0.45 TD = 0n RISE = 1
+ TARG V(Out) VAL = 0.45 FALL = 1

.MEASURE TRAN t2 TRIG V(N_1) VAL = 0.45 TD = 0n FALL = 1
+ TARG V(Out) VAL = 0.45 RISE = 1


.MEASURE TRAN tp PARAM='(t1+t2)/2.0'


.OPTION PROBE POST MEASOUT
.end
***********************************************************************
***********************************************************************
Now after writing the code save it with the extension "your_file_name.sp".




HSPICE : Now lets start to simulate your design with HSPICE.

1) Open the HSPICEpui





2) Click the OPEN Button to open the design file or the code file you wrote. Browse your design file in the design section and left rest of the thing.



3) Now click the Simulate button .

4) Now open the 'Avanwaves' to view your pulses or the output.


5) Now click the operating points you want to view like in my case i double click on vin and vout.
and  see the wave form.

6) Now click on the Editll to view your result like Power , Propagation Delay , Hold Time etc.


As you can read that the average power(avg_power) is .17 microwatt and propagation delay(tp) is about .18 ps.

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                                           Clean India
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Please share and comment if you see this tutorial informative
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CNTFET Inverter "Design & Simulation using HSPICE"

 
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