Friday, 1 May 2015

Designing of Low Power CNTFET Based D Flip-Flop using Forced Stack Technique

Low Power devices in small packages is the need of present and future electronic devices. Electronics Industry is making devices which can be planted in human bodies. CMOS Technology won‟t be able to deliver such devices because it shows short channel effects in Nano scale. So, to overcome the problems of CMOS technology we use CNTs (Carbon Nano Tubes). In electronic devices, power is consumed by various elements like flip-flop, latches, clock sources. So in order to reduce power of a system we used to reduce power consumed by flip-flops.
In this paper we design an existing flip-flop “Low power clocked pass transistor flip-flop (LCPTFF)” on CNTFET using Stanford CNTFET model for reference. We propose a design of CNTFET based Forced Stack Low Power Clocked Pass Transistor Flip-Flop (CN-FS-LCPTFF) and observe 12% to 25% power reduction in various conditions like temperature change, CNTFET diameter change, and different voltage supply.


Vikas Sharma, Umesh Dutta, “Designing of Low Power CNTFET Based D Flip-Flop Using Forced Stack Technique”Vol. 5 – Issue 4 (April – 2015), International Journal of Engineering Research and Applications (IJERA) , ISSN: 2248-9622 , www.ijera.com

About the Author

Vikas Sharma

Author & Editor

Hobbyst Researcher and working in electronics domain, M.Tech in VLSI Design and Embedded Systems.

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